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SMBus/I 2 C Interfaced 4-Port, Level-Translating
GPIOs and LED Drivers
PORT_[2]
V DD
V LA
MAX7307 ONLY
(DEBOUNCE)
PORT_[6]
(THRESHOLD
SELECT)
1
0
PORT_[0]
(PORTIN)
0
1
TRANSITION
DETECTION
INTERRUPT
LOGIC
DEBOUNCE LOGIC
TRANSITION
DETECTION
PORT_ [5]
INTERRUPT
ENABLE
I/O
INT
INT2
INT
INT4
Figure 1. Input Port Structure
Table 7. Port I/O Registers (I/O Port Set as an Output, Registers 0x01 to 0x04)
REGISTER BIT
D7
D6
D5
D4
D3
D2
D1
D0
DESCRIPTION
Port I/O Set Bit
Output Port Set to
Push-Pull
or Open-Drain
PWM/Blink Enable
Duty Cycle Bit 4
Duty Cycle Bit 3
Duty Cycle Bit 2
Duty Cycle Bit 1
Duty Cycle Bit 0
VALUE
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
FUNCTION
Sets the I/O port as an output.
Sets the output type to open-drain.
Sets the output type to push-pull.
Sets the output to PWM mode.
Sets the output to blink mode.
MSB of the 5-bit duty cycle setting. See the PWM and Blink Timing section.
MSB of the 5-bit duty cycle setting. See the PWM and Blink Timing section.
Bit 3 of the 5-bit duty cycle setting. See the PWM and Blink Timing section.
Bit 3 of the 5-bit duty cycle setting. See the PWM and Blink Timing section.
Bit 2 of the 5-bit duty cycle setting. See the PWM and Blink Timing section.
Bit 2 of the 5-bit duty cycle setting. See the PWM and Blink Timing section.
Bit 1 of the 5-bit duty cycle setting. See the PWM and Blink Timing section.
Bit 1 of the 5-bit duty cycle setting. See the PWM and Blink Timing section.
LSB of the 5-bit duty cycle setting. See the PWM and Blink Timing section.
LSB of the 5-bit duty cycle setting. See the PWM and Blink Timing section.
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